Logic Solver Suite

Boolean minimization, state machine synthesis & sequential reduction engine

Engine Active

Function Info

Parameters

Output Name

Input Names (comma-separated)

Terms

Min & Don't Care

Minterms (comma-separated)

Don't Cares (comma-separated)

Settings

Execution

Sum of Products (SOP) Product of Sums (POS)

Draw K-Map (≤ 10 vars) Draw Groupings

Solutions

Synthesized HDL

Generic Boolean

VHDL Expression

Verilog Expression

Karnaugh Map

Interactive Matrix

Function Info

Parameters

Output Name

Input Names (comma-separated)

Terms

Algorithm Input

Minterms (comma-separated)

Don't Cares (comma-separated)

Minimized Function

SOP Result

Quine-McCluskey Steps

Execution Trace

Enter function info and terms, then click 'Solve'.

Primitive Flow Table

Incompletely Specified FSM

States (M)

Inputs (N)

Results

Analysis

Results will be displayed here after solving.

Compatibility Graph

State Graph

Solve to generate the compatibility graph.

Reduced State Table

Minimal Machine

The final minimized state table will appear here.

FSM Input

Pattern Definition

String or Pattern to recognize

FSM Type

Generated FSM

State Transition Table

The generated state table will be displayed here.