Logic Solver Suite

Function Info

Output Name:

Input Names (comma-separated):

Terms

Minterms (comma-separated):

Don't Cares (comma-separated):

Settings

Sum of Products (SOP)

Product of Sums (POS)

Draw K-Map (≤ 10 vars)

Draw Groupings

Solutions

Generic:

VHDL:

Verilog:

Karnaugh Map

Function Info

Output Name:

Input Names (comma-separated):

Terms

Minterms (comma-separated):

Don't Cares (comma-separated):

Minimized Function

Quine-McCluskey Steps

Enter function info and terms, then click 'Solve'.

Primitive Flow Table

States (M):

Inputs (N):

Results

Results will be displayed here.

Compatibility Graph

Solve to generate the graph.

Reduced State Table

The final minimized table will appear here.

FSM Input

String or Pattern to recognize:

FSM Type:

Generated FSM

The generated FSM will be displayed here.